1. Field of the Invention
The present invention relates to a variable length code decoding apparatus.
2. Description of the Prior Art
Conventionally, various picture data compression techniques have been adopted. In any of these picture data compression techniques, picture data once compressed are used again after having been returned to the original picture data by extending the compressed picture data.
As one of the picture data compression and extension techniques, there exists a moving picture data compression and extension technique referred to as MPEG2 (ISO/IEC 13818-2) standard. Although not described in detail herein because being well known, this standard is disclosed in Latest MPEG Textbook! by Hiroshi FUJIWARA, 1st Edition, Published by ASCII Publication Department on Aug. 1, 1994, for instance.
FIG. 3 is a block diagram showing an example of a decoding circuit for decoding coded signals coded compressed in accordance with the MPEG standard. In the circuit shown in FIG. 3, a vdv buffer (DRAM) is added for explanation to a circuit disclosed by Data Compression and Digital Modulation! of NIKKEI ELECTRONICS BOOKS, on page 96, Published by NIKKEI BP Corp. Oct. 10, 1993.
This circuit operates as follows: when intra-frames obtained by coding intra-frame picture signals are decoded, a switch SW.sub.1 is switched to the "a" side. On the other hand, when predicted-frames/interpolated frames obtained by coding inter-frame picture signals are decoded, the switch SW.sub.1 is switched to the "b" side to add the differential picture data to the predicted picture data. In the case of the predicted frame decoding, since the switch SW.sub.1 is set to the "b" side, the decoded picture data are stored in a frame memory A at the same time when outputted. In this case, the picture data stored in the frame memory A are transferred to a frame memory B. Further, in the case of the interpolated frame decoding, a switch SW.sub.2 is set to any position of "c", "e" and "d" according to the frame prediction direction (forward /backward /both forward and backward).
When the coded signals compressed as described above are decoded, start codes are used. In more detail, since the compressed picture data are of hierarchical construction, a start code corresponding to each hierarchy is always placed at the start of each hierarchy. Therefore, when picture data are decoded, it is necessary to detect the start codes accurately. Here, two positions at which the start codes are detected can be considered in the circuit shown in FIG. 3. One position is a node "a" immediately before picture data (coded signals) are inputted to a so-called decoder body, and the other position is a node "b" immediately before the start codes are used for processing. In the case of the detection at the node "a", when the start code is byte-aligned, the start codes can be detected by use of a small-scaled circuit construction. In this case, however, since these detected start codes are once stored in the vdv buffer, a circuit for predicting the time at which the detected start codes are to be used is required. Further, where a plurality of start codes are stored in the vdv buffer, a circuit for deciding which detected output corresponds to the start code is required. As a result, the number of circuit elements inevitably increases.
In contrast with this, in the case of the detection at the "b" node, no prediction circuit is required. However, since the inputted picture data to be detected have been shifted irregularly in order to form the fixed length conversion output signals on the basis of the variable length picture data, the byte alignment has been already destroyed. Therefore, the start codes must be checked over all the pattern in unit of bit. Accordingly, the scale of the detecting circuit becomes as large as eight times, as compared with the node "a" detection at which the start codes can be detected in the byte alignment state.
FIG. 4 shows a prior art start code detecting circuit used for the node "b" detection. Although not described in detail herein because being well known, in brief, this circuit shown in FIG. 4 detects the start codes after the picture data have been converted into fixed length data. In more detail, 34-bit data already converted by a barrel shifter 11 are stored in two registers 12 and 13, respectively, and then inputted to a circuit 14 composed of 32 sets of 24-input OR circuits. The output of this circuit 14 is inputted to a 32-input OR circuit 15 to detect the start code. Therefore, the number of elements required for these circuits 14 and 15 also inevitably increases. Here, however, in the case of the "b" node detection, when the shifted data are checked one by one, although the number of circuit elements can be minimized, since the processing time of the entire picture processing LSI increases excessively, it is impossible to realize the real time decoding.
As described above, in the prior art variable length code decoding circuit as shown in FIG. 3, when the start codes are detected at the node "a", there exists a problem in that since the start codes are detected excessively earlier than actually used, the detected start codes are difficult to be used for the succeeding processing. Or else, when the start codes are detected at the node "b", there exists a problem in that since the data to be detected have been already converted into fixed length, the detected start codes are easily detected.